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Integrated Circuit Systems, Inc.
ICS94225
AMD-K7TM System Clock Chip
Recommended Application: AMD 750/760 style chipset Output Features: * 3 differential pair open drain CPU clocks (1.5V external pull-up; up to 150MHz achieviable through I2C) * 2 - AGPCLK @ 3.3V * 8 - PCI @3.3V, including 1 free running * 1 - 48MHz @ 3.3V * 1 - 24/48MHz @ 3.3V * 2- REF @3.3V, 14.318MHz. Features: * Programmable ouput frequency * Programmable ouput rise/fall time * Programmable group skew * Real time system reset output * Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage * Watchdog timer technology to reset system if over-clocking causes malfunction * Uses external 14.318MHz crystal
**FS0/REF0 **FS1/REF1 GNDREF X1 X2 GNDPCI PCICLK_F PCICLK0 VDDPCI PCICLK1 PCICLK2 GNDPCI PCICLK3 PCICLK4 VDDPCI PCICLK5 PCICLK6 VDDAGP AGP0 AGP1 GNDAGP VDD48 48MHz SEL24_48#/24-48MHz
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDREF GNDSD SDRAM_OUT VDDSD RESERVED CPUCLKC2 CPUCLKT2 GNDCPU CPUCLKC1 CPUCLKT1 GND CPUCLKC0 CPUCLKT0 RESET# VDD GND PCI_STOP# CPU_STOP# PD# SPREAD# FS2* SDATA SCLK GND48
48-Pin 300mil SSOP
* Internal 120K pullup resistor on indicated inputs ** Internal 240K pullup resistor on indicated inputs
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24_48MHz
Functionality
FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPU, SDRAM 133.33 95 100.99 115 100.7 103 105 110 PCI 33.33 31.67 33.66 38.33 33.57 34.33 35.00 36.67 AGP 66.67 63.33 67.33 76.67 67.13 68.67 70.00 73.33
REF (1:0)
CPU DIVDER
Stop
3 3
CPUCLKT (2:0) CPUCLKC (2:0) SDRAM_OUT
SDRAM DIVDER
SEL24_48# SDATA Control SCLK FS (2:0) PD# PCI_STOP# CPU_STOP# SPREAD# Config. Reg. Logic
AGP DIVDER
2
PCI DIVDER
Stop
7
PCICLK (6:0) PCICLK_F AGP (1:0)
Power Groups
VDD48, GND48 = 48MHz, PLL2 VDDREF, GNDREF= REF, X1, X2 VDD, GND = PLL Core
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ICS94225
ICS94225
General Description
The ICS94225 is a main clock synthesizer chip for AMD-K7 based systems with AMD 750/760 style chipsets. This provides all clocks required for such a system. The ICS94225 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/ enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking.
Pin Descriptions
PIN NUMBER 2,1 3, 6, 21, 25, 33, 38, 41, 47 4 5 7 17, 16, 14, 13, 11, 10, 8 9, 15 18 20, 19 34 22 23 24 26 27 28 29 30 31 32 35 46 44 42, 39, 36 43, 40, 37 45 48
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PIN NAME FS (1:0) REF (1:0) GND X1 X2 PCICLK_F PCICLK (6:0) VDDPCI VDDAGP AGP (1:0) VDD VDD48 48MHz SEL24-48# 24-48MHz SCLK SDATA FS2 SPREAD# PD# CPU_STOP# PCI_STOP#
TYPE IN OUT PWR IN OUT OUT OUT PWR PWR OUT PWR PWR OUT IN OUT IN I/O IN IN IN IN IN
DESCRIPTION Frequency Select pins, has pull-up to VDD 14.318MHz clock output Ground XTAL_IN 14.318MHz Cr ystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Cr ystal output, has internal load cap 33pF Free Running PCI output. Not affected by the PCI_STOP# input. PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Power for AGP outputs, nominally 3.3V AGP outputs defined as 2X PCI. These may not be stopped. Isolated power for core, nominally 3.3V Power for 48MHz and 24MHz outputs nominally 3.3V 48MHz output Selects 24 or 48MHz output for pin 24 Low = 48MHz High = 24MHz Fixed clock out selectable through SEL24-48# Clock pin of I2C circuitr y 5V tolerant Data pin for I2C circuitr y 5V tolerant Frequency Select pin, has pull-up to VDD Enables Spread Spectrum feature when LOW. Down Spread 0.5% modulation frequency =50KHz Powers down chip, active low. Internal PLL & all outputs are disabled. Halts CPUCLKs. CPUCLKT is driven LOW wheras CPUCLKC is driven HIGH when this pin is asser ted (Active LOW). Halts PCI Bus at logic "0" level when driven low. PCICLK_F is not affected by this pin
RESET#
SDRAM_OUT RESERVED CPUCLKT (2:0) CPUCLKC (2:0) VDDSD VDDREF
OUT
OUT N/C OUT OUT PWR PWR
Real time system reset signal for watchdog tmer timeout. This signal is active low.
Reference clock for SDRAM zero delay buffer Future CPU power rail "True" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. "Complementar y" clocks of differental pair CPU output. These open drain outputs need an external 1.5V pull_up. Power for SDRAM_OUT pin. Norminally 3.3V Power for REF, X1, X2, nominally 3.3V
2
ICS94225
Byte 1: Reserved Active/Inactive Register (1= enable, 0 = disable)
Byte 2: Reserved, Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Byte 3: Reserved Active/Inactive Register (1= enable, 0 = disable)
Byte 4: Clock Control Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
BIT
7 6 5 4 3 2 1 0
PIN# PWD
1 23 22 20 19 42, 43 39, 40 36, 37 1 1 1 1 1 1 1 1 REF0
DESCRIPTION
24MHz/48MHz USB0 AGP1 AGP0 CPUCLKC/T2 CPUCLKC/T1 CPUCLKC/T0
Byte 5: PCI Clock Control Register (1= enable, 0 = disable)
BIT
7 6 5 4 3 2 1 0
Notes:
PIN# PWD
2 17 16 14 13 11 10 8 1 1 1 1 1 1 1 1 REF1
DESCRIPTION
PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
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ICS94225
Byte 6: SDRAM Clock & Generator Mode Control Register
Bit 7
Description Spread Spectrum enable (+/- 0.25% center spread) 0=OFF 1=ON
Bit 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 Bit 6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 Bit 5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 Bit 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU, SDRAM 133.33 95 100.99 115 100.7 103 105 110 102 104 106 107 108 109 90 111 112 113 114 116 117 118 119 120 142 144 146 138 136 135 140 150 PCI 33.33 31.67 33.66 38.33 33.57 34.33 35.00 36.67 34.00 34.67 35.33 35.67 36.00 36.33 30.00 37.00 37.33 37.67 38.00 38.67 39.00 39.33 39.67 30.00 35.50 36.00 36.50 34.50 34.00 33.75 35.00 37.50 AGP 66.67 63.33 67.33 76.67 67.13 68.67 70.00 73.33 68.00 69.33 70.67 71.33 72.00 72.67 60.00 74.00 74.67 75.33 76.00 77.33 78.00 78.67 79.33 60.00 71.00 72.00 73.00 69.00 68.00 67.50 70.00 75.00
PWD 0
6:2
0010 Note1
1
0 - Frequency is selected by hardware select, latched input; Spread controlled by pin 29 1 - Frequency is selected by Bit (6:2); Spread controlled by Bit 0 - SDRAM_OUT Disable 1 - SDRAM_OUT Enable
0
0
1
Notes: 1. Default at power-up will be latched logic inputs to define frequency, as displayed by Bit 1. 2. PWD = Power-Up Default
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4
ICS94225
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 1 X X X X X
Description Vendor ID Vendor ID Vendor ID Revision ID Revision ID Revision ID Revision ID Revision ID
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 1 0 0 0
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Byte 9: Watchdog Timer Count Register
Byte 10: VCO Control Selection Bit & Watchdog Timer Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 0 0 0 0
Description The decimal representation of these 8 bits correspond to 290ms or 1ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 290ms.
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 1 0 0 0 0
Description 0=Hw/B0 freq / 1=B11 & 12 freq WD Enable 0=disable / 1=enable WD Status 0=normal / 1=alarm WD Safe Frequency, Byte 0 bit 2 WD Safe Frequency, FS3 WD Safe Frequency, FS2 WD Safe Frequency, FS1 WD Safe Frequency, FS0
Note: FS values in bit [0:4] will correspond to Byte 0 FS values. Default safe frequency is same as 00000 entry in byte0.
Byte 11: VCO Frequency Control Register
Byte 12: VCO Frequency Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit0 REF Divider Bit6 REF Divider Bit5 REF Divider Bit4 REF Divider Bit3 REF Divider Bit2 REF Divider Bit1 REF Divider Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit8 VCO Divider Bit7 VCO Divider Bit6 VCO Divider Bit5 VCO Divider Bit4 VCO Divider Bit3 VCO Divider Bit2 VCO Divider Bit1
Note: The decimal representation of these 7 bits (Byte 11 [6:0]) + 2 is equal to the REF divider value .
Notes: 1. PWD = Power on Default
Note: The decimal representation of these 9 bits (Byte 12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO divider value. For example if VCO divider value of 36 is desired, user need to program 36 - 8 = 28, namely, 0, 00011100 into byte 12 bit & byte 11 bit 7.
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5
ICS94225
Byte 13: Spread Sectrum Control Register
Byte 14:
Spread Sectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Spread Spectrum Bit7 Spread Spectrum Bit6 Spread Spectrum Bit5 Spread Spectrum Bit4 Spread Spectrum Bit3 Spread Spectrum Bit2 Spread Spectrum Bit1 Spread Spectrum Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit12 Spread Spectrum Bit11 Spread Spectrum Bit10 Spread Spectrum Bi 9 Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD Description X X CPUCLKC2/T2 Skew Control X X X X PCICLK_F Skew Control X X
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD Description X X PCICLK (6:0) Skew Control X X X X AGP (3:0) Skew Control X X
Byte 17: Output Rise/Fall Time Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description CPUCLKT0 CPUCLKC0 CPUCLKT1 CPUCLKC1 AGP (2:0) Slew Rate Control 3V66 (1:0) Slew Rate Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description PCI (3:0): Slew Rate Control PCI (6:4): Slew Rate Control 48MHz: Slew Rate Control 24MHz: Slew Rate Control
Notes: 1. PWD = Power on Default 2. The power on default for byte 13-20 depends on the harware (latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting. Be sure to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first pass. 3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up value.
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6
ICS94225
Byte 19: Reserved Register
Byte 20: Reserved Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Note: Byte 19 and 20 are reserved registers, these VCO Programming Constrains VCO Frequency ...................... 150MHz to 500MHz VCO Divider Range ................ 8 to 519 REF Divider Range ................. 2 to 129 Phase Detector Stability .......... 0.3536 to 1.4142 Useful Formula VCO Frequency = 14.31818 x VCO/REF divider value Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5 To program the VCO frequency for over-clocking. 0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming. 1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by writing to byte 0, or using initial hardware power up frequency. 2. Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20). 3. Read back byte 11-20 and copy values in these registers. 4. Re-initialize the write sequence. 5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values. 6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew rate. 7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be changed again, user only needs to write to byte 11 and 12 unless the system is to reboot. Note: 1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew relation programmed into bytes 13-16 could be unstable. Step 3 & 7 assure the correct spread and skew relationship. 2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly. 3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz). 4. ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program the VCO frequency. 5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount desired. See Application note for software support.
0445B--08/01/03
are unused registers writing to these registers will not affect device performance or functinality.
7
ICS94225
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Volt age VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS VIH Input High Voltage Input Low Voltage Input High Current Input Low Current VIL IIH IIL1 IIL2 IDD3.3OP66 Supply Current Power Down Input frequency
1
MIN 2 VSS - 0.3
TYP
MAX VDD + 0.3 0.8 5
UNITS V V A
VIN = VDD VIN =0 V; Inputs with no pull-up
Input Low Current
resistors VIN =0 V; Inputs with pull-up resistors CL =0 pF; Select@ 66MHz
CL =0 pF; Select@ 100MHz CL =0 pF; Select@ 133MHz VDD = 3.3 V Logic Inputs Logic Inputs X1 & X2 pins From VDD= 3.3 V to 1% target
-5 mA -200 87 91 104 3.25 14.318 180 5 16 5 5 27 45 3 1 2.85 4 mA mA MHz pF pF pF ms ns
IDD3.3OP100 IDD3.3OP133 PD Fi CIN CIN CINX TSTAB
12
Input Capacitance
Freq. tCPU-PCI VT = 50% to 1.5V 1 Guaranteed by design, not 100% tested in production.
0445B--08/01/03
8
ICS94225
Electrical Characteristics - USB, REF(1:0)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN VOH5 IOH = -12 mA Output High Voltage 2.4 IOL = 9 mA VOL5 Output Low Voltage VOH = 2.0 V IOH5 Output High Current IOL5 VOL = 0.8 V Output Low Current 16 1 tr5 VOL = 0.4 V, VOH = 2.4 V Rise Time 1 tf5 VOH = 2.4 V, VOL = 0.4 V Fall Time 1 dt5 VT = 1.5V 45 Duty Cycle Jitter, Cycle-to-cycle1 tjcyc-cyc2B VT = 1.5V TYP MAX 0.4 -22 0.98 0.77 54 471 4 4 57 1100 UNITS V V mA mA ns ns % ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS VO = VX Z0 Output Impedance VOH2B Output High Voltage Termination to Vpull-up(external) VOL2B Output Low Voltage VOL = 0.3 V IOL2B Output Low Current tr2B VOL = 0.3 V, VOH = 1.2 V Rise Time1 VOH = 1.2 V, VOL = 0.3 V tf2B Fall Time1 1 VDIF Note 2 Differential voltage-AC 1 VDIF Note 2 Differential voltage-DC VX Note 3 Differential Crossover 1 dt2B VT = 50% Duty Cycle 1 tsk2B VT = 50% Skew 1 tjcyc-cyc2B VT = VX Jitter, Cycle-to-cycle Jitter, Absolute1 tjabs2B VT = 50% Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input level and VCP is the "complement" input level. 3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max=(Vpullup(external)/2)+150mV MIN 1 18 0.9 0.9 Vpu +0.6 51 46 86 1100 55 200 250 250 TYP MAX 1.2 0.4 UNITS V V mA ns ns V V mV % ps ps ps
0.4 0.2 550 45
-250
0445B--08/01/03
9
ICS94225
Electrical Characteristics - PCICLK_F, PCICLK(6:0)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN VOH5 IOH = -11 mA Output High Voltage 2.6 IOL = 9.4 mA VOL5 Output Low Voltage VOH = 2.0 V IOH5 Output High Current IOL5 VOL = 0.8 V Output Low Current 19 1 tr5 VOL = 0.4 V, VOH = 2.4 V Rise Time 1 tf5 VOH = 2.4 V, VOL = 0.4 V Fall Time 1 dt5 VT = 1.5V 45 Duty Cycle 1 tsk2B VT = 1.5V Skew Jitter, Cycle-to-cycle1
1
TYP
MAX 0.4 -16
1.8 1.8 51.7 175 122
2 2 55 200 500
UNITS V V mA mA ns ns % ps ps
tjcyc-cyc2B
VT = 1.5V
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK_F, PCICLK(6:0)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN VOH5 IOH = -11 mA Output High Voltage 2.6 VOL5 IOL = 9.4 mA Output Low Voltage VOH = 2.0 V IOH5 Output High Current IOL5 VOL = 0.8 V Output Low Current 19 1 tr5 VOL = 0.4 V, VOH = 2.4 V Rise Time 1 tf5 VOH = 2.4 V, VOL = 0.4 V Fall Time 1 dt5 VT = 1.5V 45 Duty Cycle 1 tsk2B VT = 1.5V Skew Jitter, Cycle-to-cycle1
1
TYP
MAX 0.4 -16
1.8 1.8 51.7 175 122
2 2 55 200 500
UNITS V V mA mA ns ns % ps ps
tjcyc-cyc2B
VT = 1.5V
Guaranteed by design, not 100% tested in production.
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10
ICS94225
Electrical Characteristics - AGP(1:0)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH5 IOH = -18 mA 2.6 Output Low Voltage VOL5 IOL = 1.8 mA VOH = 2.0 V Output High Current IOH5 VOL = 0.8 V 19 Output Low Current IOL5 1 Rise Time tr5 VOL = 0.4 V, VOH = 2.4 V Fall Time1 tf5 VOH = 2.4 V, VOL = 0.4 V 1 Duty Cycle dt5 VT = 50% 45 1 1 Skew (window) Tsk VT = 50% Jitter, Cycle-to-cycle1 tjcyc-cyc2B VT = 50%
1
TYP
MAX 0.4 -16
1.05 1.27 50.4 12 268
1.6 1.6 55 200 500
UNITS V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM_OUT
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH3 IOH = -11 mA Output Low Voltage VOL3 IOL = 11 mA Output High Current IOH3 VOH = 2.0 V VOL = 0.8 V Output Low Current IOL3 1 Rise Time tr3 VOL = 0.4 V, VOH = 2.4 V@100MHz 1 Fall Time tf3 VOH = 2.4 V, VOL = 0.4 V@100MHz 1 Duty Cycle dt3 VT = 50% 1 Jitter, Cycle-to-cycle tjcyc-cyc3B VT = 50% @ 100MHz
1
MIN 2
TYP
MAX 0.4 -12
12 0.83 0.71 50.8 240 1.6 1.6 55 250
45
UNITS V V mA mA ns ns % ps
Guaranteed by design, not 100% tested in production.
0445B--08/01/03
11
ICS94225
General I2C serial interface information for the ICS94225 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending Byte 0 through Byte 20 (see Note) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends Byte 0 through byte 8 (default) ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). * Controller (host) will need to acknowledge each byte * Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
Byte 0
ACK
ACK
Byte 0
Byte 1
ACK
ACK
Byte 1
Byte 2
ACK
ACK
Byte 2
Byte 3
ACK
ACK
Byte 3
Byte 4
ACK
ACK
Byte 4
Byte 5
ACK
ACK
Byte 5
Byte 6
ACK
ACK If 7H has been written to B6 ACK
Byte 6
Byte 7
ACK
Byte 18
ACK
Byte 19
ACK
Byte 20
ACK
Stop Bit
If 12H has been written to B6 ACK If 13H has been written to B6 ACK If 14H has been written to B6 ACK Stop Bit
Byte18 Byte 19 Byte 20
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*See notes on the following page.
12
ICS94225
Brief I2C registers description for ICS94225 Programmable System Frequency Generator
Register Name Functionality & Frequency Select Register Output Control Registers Byte 0 Description Output frequency, hardware / I2C frequency select, spread spectrum & output enable control register. Active / inactive output control registers/latch inputs read back. Byte 11 bit[7:4] is ICS vendor id 1001. Other bits in this register designate device revision ID of this part. Writing to this register will configure byte count and how many byte will be read back. Do not write 00H to this byte. Writing to this register will configure the number of seconds for the watchdog timer to reset. Watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. This bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. These registers control the dividers ratio into the phase detector and thus control the VCO output frequency. These registers control the spread percentage amount. Increment or decrement the group skew amount as compared to the initial skew. These registers will control the output rise and fall time. PWD Default See individual byte description See individual byte description See individual byte description
1-6
Vendor ID & Revision ID Registers
7
Byte Count Read Back Register Watchdog Timer Count Register Watchdog Control Registers
8
08H
9
10H
10 Bit [6:0]
000,0000
VCO Control Selection Bit
10 Bit [7]
0
VCO Frequency Control Registers
11-12
Depended on hardware/byte 0 configuration Depended on hardware/byte 0 configuration See individual byte description See individual byte description
Spread Spectrum Control Registers Group Skews Control Registers Output Rise/Fall Time Select Registers
13-14
15-16
17-20
Notes:
1.
2. 3. 4. 5. 6.
7.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to byte 8. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
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ICS94225
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Fig. 1
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ICS94225
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS94225. All other clocks will continue to run while the CPUCLKs clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
INTERNAL CPUCLK PCICLK CPU_STOP# PD# (High)
CPUCLKT CPUCLKC
Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS94225. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state.
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ICS94225
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94225. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS94225 internally. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
CPUCLK (Internal)
PCICLK (Internal) PCICLK (Free-runningl) CPU_STOP#
PCI_STOP# PWR_DWN#
PCICLK (External)
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94225 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS94225. 3. All other clocks continue to run undisturbed. 4. PD# and CPU_STOP# are shown in a high (true) state.
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ICS94225
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT CPUCLKC
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94225 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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ICS94225
N
c
L
SYMBOL A A1 b c D E E1 e h L N
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS94225yF-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS, AV = Standard Device
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